Felicia has over 27 years working with semiconductor design and processing technologies during which Ms. James held senior management posts at several major companies. She was previously the Analog Strategy Director at Dongbu HiTek's Analog Foundry Business Unit (AFBU).

Prior to this position, Felicia was a vice president at Cadence Design System for 5 years. During her role as the vice president and general manager of the Virtuoso custom design platform, she drove significant improvements in the industry leading analog design platform including the release of a well-received quality and performance focused version as well as initiating the next generation platform that incorporated innovative technologies from several acquired companies as well as major new development efforts. In that role, Ms. James was focused on improving productivity and silicon accuracy for the leading technology's well-established customer base.

Earlier in her career, Felicia worked at Texas Instruments over an 18-year period during which she distinguished herself in a number of key positions in Product Engineering, IC Design, and EDA.

Ms. James is widely recognized as an industry expert in the area of mixed-signal IC product development. Ms. James holds a B.S. degree in Electrical Engineering from the University of Virginia in 1983 and an EMBA from the University of Texas in 2000.

Prior to starting Zipalog Inc., Michael worked at Texas Instruments for 11 years. Michael managed the development of TI's internal Cadence-based analog-centric design tool flow. As part of this position, Michael managed the definition and development of TI's internal EDA tools, like TISPICE4, Sparks, and CAPS. TISPICE4 is a complete rewrite of TI's internal SPICE simulation program that offers simulation performance improvements, a more complete reliability analysis capability, and facilitates mixed-signal transient simulation (AMS). Sparks is an innovative tool that utilizes topology-based rules to identify ESD and design problems in top-level netlists. CAPS is a collaborative analog IP development framework.

Before becoming a manager at TI, Michael was the principle software developer for TI's internal transistor-level statistical design and optimization software. Michael has experience modeling analog circuits with Verilog-A and provided support for both modeling and simulation performance for teams developing system level models. With detailed understanding both of analog design as well as complex analysis and modeling and computational tools, Michael's unique skill set helps drive innovation and performance improvements in design methodology.

Michael received his B.S. degree in Electrical Engineering from the University of Virginia (with Highest Distinction) and M.S. and Ph.D. degrees in Electrical and Computer Engineering from Carnegie Mellon University. As a graduate student, he was a Semiconductor Research Corporation (SRC) Fellow.